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| KSZ8041NL 10Base-T/100Base-TX Physical Layer Transceiver General Description The KSZ8041NL is a single supply 10Base-T/100Base-TX Physical Layer Transceiver, which provides MII/RMII interfaces to transmit and receive data. An unique mixed signal design extends signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. The KSZ8041NL represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10Base-T/100Base-TX applications. The KSZ8041NL comes in a 32-pin, lead-free MLF(R) (QFN per JDEC) package (See Ordering Information). Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com. Functional Diagram MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com October 2006 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Features * Single-chip 10Base-T/100Base-TX physical layer solution * Fully compliant to IEEE 802.3u Standard * Low power CMOS design, power consumption of <180mW * HP auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option * Robust operation over standard cables * Power down and power saving modes * MII interface support * RMII interface support with external 50MHz system clock * MIIM (MDC/MDIO) management bus for PHY register configuration * Interrupt pin option * Programmable LED outputs for link, activity and speed * ESD rating (6kV) * Single power supply (3.3V) * Built-in 1.8V regulator for core * Available in 32-pin (5mm x 5mm) MLF(R) package Applications * * * * * * Printer LOM Game Console IPTV IP Phone IP Set-top Box Ordering Information Part Number KSZ8041NL KSZ8041NLI Temp. Range 0C to 70C -40C to 85C Package 32-Pin MLF 32-Pin MLF (R) (R) Lead Finish Pb-Free Pb-Free October 2006 2 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Revision History Revision 1.0 Date 10/13/06 Summary of Changes Data sheet created October 2006 3 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Contents Pin Configuration .................................................................................................................................................................. 8 Pin Description ...................................................................................................................................................................... 9 Strapping Options............................................................................................................................................................... 12 Functional Description ....................................................................................................................................................... 13 100Base-TX Transmit....................................................................................................................................................... 13 100Base-TX Receive........................................................................................................................................................ 13 PLL Clock Synthesizer...................................................................................................................................................... 13 Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 13 10Base-T Transmit ........................................................................................................................................................... 13 10Base-T Receive ............................................................................................................................................................ 13 SQE and Jabber Function (10Base-T only)...................................................................................................................... 14 Auto-Negotiation ............................................................................................................................................................... 14 MII Management (MIIM) Interface .................................................................................................................................... 16 Interrupt (INTRP) .............................................................................................................................................................. 16 MII Data Interface ............................................................................................................................................................. 16 MII Signal Definition.......................................................................................................................................................... 17 Transmit Clock (TXC) ...................................................................................................................................................................17 Transmit Enable (TXEN)..............................................................................................................................................................17 Transmit Data [3:0] (TXD[3:0]) ...................................................................................................................................................17 Receive Clock (RXC) .....................................................................................................................................................................17 Receive Data Valid (RXDV) ..........................................................................................................................................................18 Receive Data [3:0] (RXD[3:0])......................................................................................................................................................18 Receive Error (RXER)...................................................................................................................................................................18 Carrier Sense (CRS) ......................................................................................................................................................................18 Collision (COL) .............................................................................................................................................................................18 Reduced MII (RMII) Data Interface................................................................................................................................... 18 RMII Signal Definition ....................................................................................................................................................... 19 Reference Clock (REF_CLK) .......................................................................................................................................................19 Transmit Enable (TX_EN)............................................................................................................................................................19 Transmit Data [1:0] (TXD[1:0]) ...................................................................................................................................................19 Carrier Sense/Receive Data Valid (CRS_DV) ..............................................................................................................................19 Receive Data [1:0] (RXD[1:0])......................................................................................................................................................19 Receive Error (RX_ER).................................................................................................................................................................19 Collision Detection ........................................................................................................................................................................20 HP Auto MDI/MDI-X.......................................................................................................................................................... 20 Straight Cable ................................................................................................................................................................................20 Crossover Cable .............................................................................................................................................................................21 Power Management.......................................................................................................................................................... 22 Power Saving Mode.......................................................................................................................................................................22 Power Down Mode ........................................................................................................................................................................22 Reference Clock Connection Options............................................................................................................................... 22 October 2006 4 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Reference Circuit for Power and Ground Connections .................................................................................................... 23 Register Map........................................................................................................................................................................ 24 Register Description ........................................................................................................................................................... 24 Absolute Maximum Ratings(1) ............................................................................................................................................ 31 Operating Ratings(2) ............................................................................................................................................................ 31 Electrical Characteristics(4) ................................................................................................................................................ 31 Timing Diagrams ................................................................................................................................................................. 33 MII SQE Timing (10Base-T) ............................................................................................................................................. 33 MII Transmit Timing (10Base-T) ....................................................................................................................................... 34 MII Receive Timing (10Base-T) ........................................................................................................................................ 35 MII Transmit Timing (100Base-TX)................................................................................................................................... 36 MII Receive Timing (100Base-TX).................................................................................................................................... 37 RMII Timing....................................................................................................................................................................... 38 Auto-Negotiation Timing ................................................................................................................................................... 39 MDC/MDIO Timing............................................................................................................................................................ 40 Reset Timing..................................................................................................................................................................... 41 Reset Circuit ........................................................................................................................................................................ 42 Reference Circuits for LED Strapping Pins...................................................................................................................... 43 Selection of Isolation Transformer.................................................................................................................................... 44 Selection of Reference Crystal .......................................................................................................................................... 44 Package Information........................................................................................................................................................... 45 October 2006 5 M9999-102406-1.0 Micrel, Inc. KSZ8041NL List of Figures Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 15 Figure 2. Typical Straight Cable Connection ....................................................................................................................... 20 Figure 3. Typical Crossover Cable Connection ................................................................................................................... 21 Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode ................................................................................... 22 Figure 5. 50MHz Oscillator Reference Clock for RMII Mode............................................................................................... 22 Figure 6. KSZ8041NL Power and Ground Connections...................................................................................................... 23 Figure 7. MII SQE Timing (10Base-T) ................................................................................................................................. 33 Figure 8. MII Transmit Timing (10Base-T) ........................................................................................................................... 34 Figure 9. MII Receive Timing (10Base-T) ............................................................................................................................ 35 Figure 10. MII Transmit Timing (100Base-TX)..................................................................................................................... 36 Figure 11. MII Receive Timing (100Base-TX)...................................................................................................................... 37 Figure 12. RMII Timing - Data Received from RMII ............................................................................................................ 38 Figure 13. RMII Timing - Data Input to RMII ....................................................................................................................... 38 Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 39 Figure 15. MDC/MDIO Timing.............................................................................................................................................. 40 Figure 16. Reset Timing....................................................................................................................................................... 41 Figure 17. Recommended Reset Circuit.............................................................................................................................. 42 Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 42 Figure 19. Reference Circuits for LED Strapping Pins......................................................................................................... 43 October 2006 6 M9999-102406-1.0 Micrel, Inc. KSZ8041NL List of Tables Table 1. MII Management Frame Format ............................................................................................................................ 16 Table 2. MII Signal Definition ............................................................................................................................................... 17 Table 3. RMII Signal Description.......................................................................................................................................... 19 Table 4. MDI/MDI-X Pin Definition ....................................................................................................................................... 20 Table 5. KSZ8041NL Power Pin Description ....................................................................................................................... 23 Table 6. MII SQE Timing (10Base-T) Parameters ............................................................................................................... 33 Table 7. MII Transmit Timing (10Base-T) Parameters ........................................................................................................ 34 Table 8. MII Receive Timing (10Base-T) Parameters ......................................................................................................... 35 Table 9. MII Transmit Timing (100Base-TX) Parameters .................................................................................................... 36 Table 10. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 37 Table 11. RMII Timing Parameters ...................................................................................................................................... 38 Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 39 Table 13. MDC/MDIO Timing Parameters ........................................................................................................................... 40 Table 14. Reset Timing Parameters .................................................................................................................................... 41 Table 15. Transformer Selection Criteria ............................................................................................................................. 44 Table 16. Qualified Single Port Magnetics........................................................................................................................... 44 Table 17. Typical Reference Crystal Characteristics ........................................................................................................... 44 October 2006 7 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Pin Configuration 32-Pin (5mm x 5mm) MLF (R) October 2006 8 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Pin Description Pin Number 1 2 3 4 5 6 7 8 Pin Name GND VDDPLL_1.8 VDDA_3.3 RXRX+ TXTX+ XO Type Gnd P P I/O I/O I/O I/O O (1) Pin Function Ground 1.8V analog VDD 3.3V analog VDD Physical receive or transmit signal (- differential) Physical receive or transmit signal (+ differential) Physical transmit or receive signal (- differential) Physical transmit or receive signal (+ differential) Crystal feedback This pin is used only in MII mode when a 25 MHz crystal is used. This pin is a no connect if oscillator or external clock source is used, or if RMII mode is selected. 9 XI / REFCLK I Crystal / Oscillator / External Clock Input MII Mode: RMII Mode: 25MHz +/-50ppm (crystal, oscillator, or external clock) 50MHz +/-50ppm (oscillator, or external clock only) 10 11 12 13 REXT MDIO MDC RXD3 / PHYAD0 I/O I/O I Ipu/O Set physical transmit output current Pull-down this pin with a 6.49K resistor to ground. Management Interface (MII) Data I/O This pin requires an external 4.7K pull-up resistor. Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface. MII Mode: Config Mode: Receive Data Output[3] (2) / The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See "Strapping Options" section for details. Receive Data Output[2] (2) 14 RXD2 / PHYAD1 Ipd/O MII Mode: Config Mode: / The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See "Strapping Options" section for details. Receive Data Output[1] Receive Data Output[1] (2) (3) 15 RXD1 / RXD[1] / PHYAD2 Ipd/O MII Mode: RMII Mode: Config Mode: / / The pull-up/pull-down value is latched as PHYADDR[2] during power-up / reset. See "Strapping Options" section for details. Receive Data Output[0] Receive Data Output[0] (2) (3) 16 RXD0 / RXD[0] / DUPLEX Ipu/O MII Mode: RMII Mode: Config Mode: / / Latched as DUPLEX (register 0h, bit 8) during power-up / reset. See "Strapping Options" section for details. Receive Data Valid Output / Carrier Sense/Receive Data Valid Output / The pull-up/pull-down value is latched as CONFIG2 during power-up / reset. See "Strapping Options" section for details. Receive Clock Output 17 18 VDDIO_3.3 RXDV / CRSDV / CONFIG2 P Ipd/O 3.3V digital VDD MII Mode: RMII Mode: Config Mode: 19 RXC O MII Mode: October 2006 9 M9999-102406-1.0 Micrel, Inc. KSZ8041NL 20 RXER / RX_ER / ISO Ipd/O MII Mode: RMII Mode: Config Mode: Receive Error Output / Receive Error Output / The pull-up/pull-down value is latched as ISOLATE during power-up / reset. See "Strapping Options" section for details. 21 INTRP Opu Interrupt Output: Programmable Interrupt Output Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active low (default) or active high. 22 23 24 TXC TXEN / TX_EN TXD0 / TXD[0] O I I MII Mode: MII Mode: RMII Mode: MII Mode: RMII Mode: Transmit Clock Output Transmit Enable Input / Transmit Enable Input Transmit Data Input[0] Transmit Data Input[0] Transmit Data Input[1] Transmit Data Input[1] Transmit Data Input[2] Transmit Data Input[3] (4) (5) (4) (5) (4) (4) / 25 TXD1 / TXD[1] I MII Mode: RMII Mode: / 26 27 28 TXD2 TXD3 COL / CONFIG0 I I Ipd/O MII Mode: MII Mode: MII Mode: Config Mode: / / Collision Detect Output / The pull-up/pull-down value is latched as CONFIG0 during power-up / reset. See "Strapping Options" section for details. Carrier Sense Output / The pull-up/pull-down value is latched as CONFIG1 during power-up / reset. See "Strapping Options" section for details. Programmable LED0 Output / Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up / reset. See "Strapping Options" section for details. 29 CRS / CONFIG1 Ipd/O MII Mode: Config Mode: 30 LED0 / NWAYEN Ipu/O LED Output: Config Mode: The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity No Link Link Activity LED mode = [01] Link No Link Link LED mode = [10] Reserved LED mode = [11] Reserved Pin State H L LED Definition OFF ON Pin State H L Toggle LED Definition OFF ON Blinking October 2006 10 M9999-102406-1.0 Micrel, Inc. KSZ8041NL 31 LED1 / SPEED Ipu/O LED Output: Config Mode: Programmable LED1 Output / Latched as SPEED (register 0h, bit 13) during power-up / reset. See "Strapping Options" section for details. The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Speed 10BT 100BT LED mode = [01] Activity No Activity Activity LED mode = [10] Reserved LED mode = [11] Reserved 32 PADDLE Notes: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipd = Input with internal pull-down. Ipu = Input with internal pull-up. Opu = Output with internal pull-up. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise. 2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII. RXD[3..0] is invalid when RXDV is de-asserted. 3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY. 4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-asserted. 5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC. Pin State H L LED Definition OFF ON Pin State H L LED Definition OFF ON RST# GND I Gnd Chip Reset (active low) Ground October 2006 11 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Strapping Options Pin Number 15 14 13 18 29 28 Pin Name PHYAD2 PHYAD1 PHYAD0 CONFIG2 CONFIG1 CONFIG0 Type Ipd/O Ipd/O Ipu/O Ipd/O Ipd/O Ipd/O CONFIG[2:0] 000 001 010 011 100 101 110 111 20 ISO Ipd/O ISOLATE mode Pull-up = Enable Pull-down (default) = Disable During power-up / reset, this pin value is latched into register 0h bit 10. 31 SPEED Ipu/O SPEED mode Pull-up (default) = 100Mbps Pull-down = 10Mbps During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability support. 16 DUPLEX Ipu/O DUPLEX mode Pull-up (default) = Full Duplex Pull-down = Half Duplex During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Duplex capability support. 30 NWAYEN Ipu/O Nway Auto-Negotiation Enable Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. Note: 1. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise. (1) Pin Function The PHY Address is latched at power-up / reset and is configurable to any value from 1 to 7. The default PHY Address is 00001. PHY Address bits [4:3] are always set to `00'. The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as follows: Mode MII (default) RMII Reserved - not used Reserved - not used PCS Loopback Reserved - not used Reserved - not used Reserved - not used Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE or PCS Loopback mode, or is not configured with an incorrect PHY Address. October 2006 12 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Functional Description The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification. On the media side, the KSZ8041NL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. 100Base-TX Transmit The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The waveshaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers. 100Base-TX Receive The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KSZ8041NL generates 125Mz, 25Mz and 20Mz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50MHz oscillator or system clock. Scrambler/De-scrambler (100Base-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. 10Base-T Transmit The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic. The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and October 2006 13 M9999-102406-1.0 Micrel, Inc. KSZ8041NL RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8041NL decodes a data frame. The receive clock is kept active during idle periods in between data reception. SQE and Jabber Function (10Base-T only) In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the 10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BaseT transmitter is re-enabled and COL is de-asserted (returns to low). Auto-Negotiation The KSZ8041NL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Autonegotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12). Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest. * * * Priority 1: 100Base-TX, full-duplex Priority 2: 100Base-TX, half-duplex Priority 3: 10Base-T, full-duplex * Priority 4: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8041NL link partner is forced to bypass auto-negotiation, the KSZ8041NL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8041NL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart. October 2006 14 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Start Auto Negotiation Force Link Setting N o Parallel Operation Yes Bypass Auto Negotiation and Set Link Mode Attempt Auto Negotiation Listen for 100BASE-TX Idles Listen for 10BASE-T Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set Figure 1. Auto-Negotiation Flow Chart October 2006 15 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MII Management (MIIM) Interface The KSZ8041NL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8041NL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Additional details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification. The MIIM interface consists of the following: * * A physical connection that incorporates the clock line (MDC) and the data line (MDIO). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more KSZ8041NL devices. Each KSZ8041NL device is assigned a PHY address between 1 and 7 by the PHYAD[2:0] strapping pins. An internal addressable set of thirteen 16-bit MDIO registers. Register [0:6] are required, and their functions are defined by the IEEE 802.3u Specification. The additional registers are provided for expanded functionality. The KSZ8041NL supports MIIM in both MII mode and RMII mode. The following table shows the MII Management frame format for the KSZ8041NL. Preamble Start of Frame Read/Write OP Code 10 01 PHY Address Bits [4:0] Read Write 32 1's 32 1's 01 01 00AAA 00AAA REG Address Bits [4:0] RRRRR RRRRR Z0 10 DDDDDDDD_DDDDDDDD DDDDDDDD_DDDDDDDD Z Z TA Data Bits [15:0] Idle * Table 1. MII Management Frame Format Interrupt (INTRP) INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8041NL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh. Bit 9 of register 1Fh sets the interrupt level to active high or active low. MII Data Interface The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Specification. It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: * * * * Supports 10Mbps and 100Mbps data rates. Uses a 25MHz reference clock, sourced by the PHY. Provides independent 4-bit wide (nibble) transmit and receive data paths. Contains two distinct groups of signals: one for transmission and the other for reception. By default, the KSZ8041NL is configured in MII mode after it is power-up or reset with the following: * * A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI. CONFIG[2:0] (pins 18, 29, 28) set to `000' (default setting). October 2006 16 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MII Signal Definition The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information. Direction (with respect to PHY, KSZ8041NL signal) Output Input Input Output Output Output Output Output Output MII Signal Name TXC TXEN TXD[3:0] RXC RXDV RXD[3:0] RXER CRS COL Direction (with respect to MAC) Input Output Output Input Input Input Input, or (not required) Input Input Description Transmit Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) Transmit Enable Transmit Data [3:0] Receive Clock (2.5MHz for 10Mbps; 25MHz for 100Mbps) Receive Data Valid Receive Data [3:0] Receive Error Carrier Sense Collision Detection Table 2. MII Signal Definition Transmit Clock (TXC) TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. Transmit Enable (TXEN) TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated prior to the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC. Transmit Data [3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. TXD[3:0] is "00" to indicate idle when TXEN is de-asserted. Values other than "00" on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. Receive Clock (RXC) RXC provides the timing reference for RXDV, RXD[3:0], and RXER. * * In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY's reference clock when the line is idle, or link is down. In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY's reference clock. RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. October 2006 17 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. * In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), "5D", and remains asserted until the end of the frame. * In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXC. Receive Data [3:0] (RXD[3:0]) RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. Receive Error (RXER) RXER is asserted for one or more RXC periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC. Carrier Sense (CRS) CRS is asserted and de-asserted as follows: * * In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the reception of an end-of-frame (EOF) marker. In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE symbols are received without /T/R. Collision (COL) COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is used to inform the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with respect to TXC and RXC. Reduced MII (RMII) Data Interface The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: * * * * Supports 10Mbps and 100Mbps data rates. Uses a single 50MHz reference clock provided by the MAC or the system board. Provides independent 2-bit wide (di-bit) transmit and receive data paths. Contains two distinct groups of signals: one for transmission and the other for reception. The KSZ8041NL is configured in RMII mode after it is power-up or reset with the following: * * A 50MHz reference clock connected to REFCLK (pin 9). CONFIG[2:0] (pins 18, 29, 28) set to `001'. In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground. October 2006 18 M9999-102406-1.0 Micrel, Inc. RMII Signal Definition The following table describes the RMII signals. Refer to RMII Specification for detailed information. Direction (with respect to PHY, KSZ8041NL signal) Input Input Input Output Output Output KSZ8041NL RMII Signal Name REF_CLK TX_EN TXD[1:0] CRS_DV RXD[1:0] RX_ER Direction (with respect to MAC) Input, or Output Output Output Input Input Input, or (not required) Description Synchronous 50 MHz clock reference for receive, transmit and control interface Transmit Enable Transmit Data [1:0] Carrier Sense/Receive Data Valid Receive Data [1:0] Receive Error Table 3. RMII Signal Description Reference Clock (REF_CLK) REF_CLK is sourced by the MAC or system board. It is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER. Transmit Enable (TX_EN) TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK. Transmit Data [1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] is "00" to indicate idle when TX_EN is de-asserted. Values other than "00" on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in 100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV. So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place. Receive Data [1:0] (RXD[1:0]) RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other than "00" on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC. Receive Error (RX_ER) RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC. October 2006 19 M9999-102406-1.0 Micrel, Inc. Collision Detection The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV. KSZ8041NL HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041NL and its link partner. This feature allows the KSZ8041NL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL accordingly. HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1F bit 13. MDI and MDI-X mode is selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X. The IEEE 802.3u Standard defines MDI and MDI-X as follow: MDI RJ-45 Pin 1 2 3 6 Signal TD+ TDRD+ RDRJ-45 Pin 1 2 3 6 MDI-X Signal RD+ RDTD+ TD- Table 4. MDI/MDI-X Pin Definition Straight Cable A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). 10/100 Ethernet Media Dependent Interface 10/100 Ethernet Media Dependent Interface 1 Transmit Pair 2 3 4 Receive Pair 5 6 7 8 Straight Cable 1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8 Modular Connector (RJ-45) NIC Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 2. Typical Straight Cable Connection October 2006 20 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Crossover Cable A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The following diagram depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices). 10/100 Ethernet Media Dependent Interface 10/100 Ethernet Media Dependent Interface 1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8 Crossover Cable 1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8 Modular Connector (RJ-45) HUB (Repeater or Switch) Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 3. Typical Crossover Cable Connection October 2006 21 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Power Management The KSZ8041NL offers the following power management modes: Power Saving Mode This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode is enabled, cable is disconnected, and register 1F bit 10 is set to 1 (default setting). Under power saving mode, the KSZ8041NL shuts down all transceiver blocks, except for energy detect and PLL circuits. Additionally, in MII mode, the RXC clock output is disabled. RXC clock is enabled after the cable is connected and link is established. Power saving mode is disabled by writing a zero to register 1F bit 10. Power Down Mode This mode is used to power down the entire KSZ8041NL device when it is not in use. Power down mode is enabled by writing a one to register 0 bit 11. In the power down state, the KSZ8041NL disables all internal functions, except for the MII management interface. Reference Clock Connection Options A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL. The reference clock is 25MHz for MII mode and 50MHz for RMII mode. The following two figures illustrate how to connect the reference clock to XI / REFCLK (pin 9) and XO (pin 8) of the KSZ8041NL. Figure 4. 25MHz Crystal / Oscillator Reference Clock for MII Mode Figure 5. 50MHz Oscillator Reference Clock for RMII Mode October 2006 22 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Reference Circuit for Power and Ground Connections The KSZ8041NL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in the following figure and table. Figure 6. KSZ8041NL Power and Ground Connections Power Pin VDDPLL_1.8 VDDA_3.3 VDDIO_3.3 Pin Number 2 3 17 Description Decouple with 10uF and 0.1uF capacitors-to-ground. Connect to board's 3.3V supply through ferrite bead. Connect to board's 3.3V supply. Table 5. KSZ8041NL Power Pin Description October 2006 23 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Register Map Register Number (Hex) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h - 14h 15h 16h - 1Ah 1Bh 1Ch - 1Dh 1Eh 1Fh Description Basic Control Basic Status PHY Identifier 1 PHY Identifier 2 Auto-Negotiation Advertisement Auto-Negotiation Link Partner Ability Auto-Negotiation Expansion Auto-Negotiation Next Page Link Partner Next Page Ability Reserved RXER Counter Reserved Interrupt Control/Status Reserved PHY Control 1 PHY Control 2 Register Description Address Name Description Mode (1) Default Register 0h - Basic Control 0.15 Reset 1 = Software reset 0 = Normal operation This bit is self-cleared after a `1' is written to it. 0.14 0.13 Loop-back Speed Select (LSB) 1 = Loop-back mode 0 = Normal operation 1 = 100Mbps 0 = 10Mbps This bit is ignored if auto-negotiation is enabled (register 0.12 = 1). 0.12 AutoNegotiation Enable 1 = Enable auto-negotiation process 0 = Disable auto-negotiation process If enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. 1 = Power down mode 0 = Normal operation 0.10 Isolate 1 = Electrical isolation of PHY from MII and TX+/TX0 = Normal operation 0.9 Restart AutoNegotiation 1 = Restart auto-negotiation process 0 = Normal operation. This bit is self-cleared after a `1' is written to it. RW/SC RW Set by ISO strapping pin. See "Strapping Options" section for details. 0 RW RW RW Set by SPEED strapping pin. See "Strapping Options" section for details. Set by NWAYEN strapping pin. See "Strapping Options" section for details. 0 RW 0 RW/SC 0 0.11 Power Down October 2006 24 M9999-102406-1.0 Micrel, Inc. Address 0.8 Name Duplex Mode Description 1 = Full-duplex 0 = Half-duplex 0.7 0.6:1 0.0 Collision Test Reserved Disable Transmitter Register 1h - Basic Status 1.15 1.14 1.13 1.12 1.11 1.10:7 1.6 1.5 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved No Preamble AutoNegotiation Complete Remote Fault AutoNegotiation Ability Link Status Jabber Detect Extended Capability 1 = Preamble suppression 0 = Normal preamble 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed 1 = Remote fault 0 = No remote fault 1.3 1 = Capable to perform auto-negotiation 0 = Not capable to perform auto-negotiation 1 = Link is up 0 = Link is down 1.1 1.0 1 = Jabber detected 0 = Jabber not detected (default is low) 1 = Supports extended capabilities registers RO 1 RO/LH 0 RO/LL 0 RO 1 RO/LH 0 RO 0 1 = T4 capable 0 = Not T4 capable 1 = Capable of 100Mbps full-duplex 0 = Not capable of 100Mbps full-duplex 1 = Capable of 100Mbps half-duplex 0 = Not capable of 100Mbps half-duplex 1 = Capable of 10Mbps full-duplex 0 = Not capable of 10Mbps full-duplex 1 = Capable of 10Mbps half-duplex 0 = Not capable of 10Mbps half-duplex RO RO 0000 1 RO 1 RO 1 RO 1 RO 1 RO 0 0 = Enable transmitter 1 = Disable transmitter 1 = Enable COL test 0 = Disable COL test RO RW 000_000 0 RW Mode RW (1) KSZ8041NL Default Set by DUPLEX strapping pin. See "Strapping Options" section for details. 0 1.4 1.2 Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). Kendin Communication's OUI is 0010A1 (hex) RO 0022h October 2006 25 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Register 3h - PHY Identifier 2 3.15:10 PHY ID Number Model Number Revision Number Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication's OUI is 0010A1 (hex) Six bit manufacturer's model number Four bit manufacturer's model number RO 0001_01 3.9:4 3.3:0 RO RO 00_0000 - Register 4h - Auto-Negotiation Advertisement 4.15 4.14 4.13 4.12:11 4.10 4.9 4.8 Next Page Reserved Remote Fault Reserved Pause 100Base-T4 100Base-TX Full-Duplex 1 = PAUSE function supported 0 = No PAUSE function supported 1 = T4 capable 0 = No T4 capability 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RW Set by SPEED & DUPLEX strapping pins. See "Strapping Options" section for details. 4.7 100Base-TX Half-Duplex 10Base-T Full-Duplex 10Base-T Half-Duplex Selector Field 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability [00001] = IEEE 802.3 RW 0_0001 RW RW RW Set by SPEED strapping pin. See "Strapping Options" section for details. Set by DUPLEX strapping pin. See "Strapping Options" section for details. 1 RO 0 1 = Remote fault supported 0 = No remote fault RO RW 00 0 1 = Next page capable 0 = No next page capability. RO RW 0 0 RW 0 4.6 4.5 4.4:0 Register 5h - Auto-Negotiation Link Partner Ability 5.15 5.14 5.13 5.12 5.11:10 Next Page Acknowledge Remote Fault Reserved Pause [00] = No PAUSE [10] = Asymmetric PAUSE [01] = Symmetric PAUSE [11] = Asymmetric & Symmetric PAUSE 5.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 1 = Next page capable 0 = No next page capability 1 = Link code word received from partner 0 = Link code word not yet received 1 = Remote fault detected 0 = No remote fault RO RO 0 00 RO 0 RO 0 RO 0 October 2006 26 M9999-102406-1.0 Micrel, Inc. 5.8 5.7 5.6 5.5 5.4:0 100Base-TX Full-Duplex 100Base-TX Half-Duplex 10Base-T Full-Duplex 10Base-T Half-Duplex Selector Field 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability [00001] = IEEE 802.3 RO 0_0001 RO 0 RO 0 RO 0 RO 0 KSZ8041NL Register 6h - Auto-Negotiation Expansion 6.15:5 6.4 6.3 Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner AutoNegotiation Able 1 = Fault detected by parallel detection 0 = No fault detected by parallel detection. 1 = Link partner has next page capability 0 = Link partner does not have next page capability 1 = Local device has next page capability 0 = Local device does not have next page capability 1 = New page received 0 = New page not received yet 6.0 1 = Link partner has auto-negotiation capability 0 = Link partner does not have auto-negotiation capability RO 0 RO/LH 0 RO 1 RO 0 RO RO/LH 0000_0000_000 0 6.2 6.1 Register 7h - Auto-Negotiation Next Page 7.15 7.14 7.13 7.12 7.11 Next Page Reserved Message Page Acknowledge2 Toggle 1 = Message page 0 = Unformatted page 1 = Will comply with message 0 = Cannot comply with message 1 = Previous value of the transmitted link code word equaled logic one 0 = Logic zero 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001 RO 0 RW 0 1 = Additional next page(s) will follow 0 = Last page RO RW 0 1 RW 0 Register 8h - Link Partner Next Page Ability 8.15 8.14 8.13 Next Page Acknowledge Message Page 1 = Additional Next Page(s) will follow 0 = Last page 1 = Successful receipt of link word 0 = No successful receipt of link word 1 = Message page 0 = Unformatted page RO 0 RO 0 RO 0 October 2006 27 M9999-102406-1.0 Micrel, Inc. 8.12 8.11 Acknowledge2 Toggle 1 = Able to act on the information 0 = Not able to act on the information 1 = Previous value of transmitted link code word equal to logic zero 0 = Previous value of transmitted link code word equal to logic one 8.10:0 Message Field RO 000_0000_0000 RO 0 RO 0 KSZ8041NL Register 15h - RXER Counter 15.15:0 RXER Counter RX error counter for RX_ER frames RO/SC 0000h Register 1Bh - Interrupt Control/Status 1b.15 Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Enable Link Up Interrupt Enable Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt 1 = Enable Jabber Interrupt 0 = Disable Jabber Interrupt 1 = Enable Receive Error Interrupt 0 = Disable Receive Error Interrupt 1 = Enable Page Received Interrupt 0 = Disable Page Received Interrupt 1 = Enable Parallel Detect Fault Interrupt 0 = Disable Parallel Detect Fault Interrupt 1 = Enable Link Partner Acknowledge Interrupt 0 = Disable Link Partner Acknowledge Interrupt 1= Enable Link Down Interrupt 0 = Disable Link Down Interrupt 1 = Enable Remote Fault Interrupt 0 = Disable Remote Fault Interrupt 1 = Enable Link Up Interrupt 0 = Disable Link Up Interrupt 1 = Jabber occurred 0 = Jabber did not occurred 1 = Receive Error occurred 0 = Receive Error did not occurred 1 = Page Receive occurred 0 = Page Receive did not occurred 1 = Parallel Detect Fault occurred 0 = Parallel Detect Fault did not occurred 1= Link Partner Acknowledge occurred 0= Link Partner Acknowledge did not occurred 1= Link Down occurred 0= Link Down did not occurred 1= Remote Fault occurred 0= Remote Fault did not occurred RO/SC 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 1b.14 1b.13 1b.12 1b.11 1b.10 1b.9 1b.8 1b.7 1b.6 1b.5 1b.4 1b.3 1b.2 1b.1 October 2006 28 M9999-102406-1.0 Micrel, Inc. 1b.0 Link Up Interrupt 1= Link Up occurred 0= Link Up did not occurred RO/SC 0 KSZ8041NL Register 1Eh - PHY Control 1 1e:15:14 LED mode [00] = LED1 : Speed LED0 : Link/Activity [01] = LED1 : Activity LED0 : Link [10] = Reserved [11] = Reserved 1e.13 1e.12 1e.11 1e:10:8 1e:7 1e:6:0 Polarity Reserved MDI/MDI-X State Reserved Remote loopback Reserved 0 = Normal mode 1 = Remote (analog) loop back is enable RW 0 0 = MDI 1 = MDI-X 0 = Polarity is not reversed 1 = Polarity is reversed RO RO 0 RO RW 00 Register 1Fh - PHY Control 2 1f:15 1f:14 HP_MDIX MDI/MDI-X Select 0 = Micrel Auto MDI/MDI-X mode 1 = HP Auto MDI/MDI-X mode When Auto MDI/MDI-X is disabled, 0 = MDI Mode Transmit on TX+/- (pins 7,6) and Receive on RX+/- (pins 5,4) 1 = MDI-X Mode Transmit on RX+/- (pins 5,4) and Receive on TX+/- (pins 7,6) 1f:13 1f.12 Pairswap Disable Energy Detect 1 = Disable auto MDI/MDI-X 0 = Enable auto MDI/MDI-X 1 = Presence of signal on RX+/- analog wire pair 0 = No signal detected on RX+/1f.11 Force Link 1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. RW 0 RO 0 RW 0 RW 0 RW 1 October 2006 29 M9999-102406-1.0 Micrel, Inc. 1f.10 Power Saving 1 = Enable power saving 0 = Disable power saving If power saving mode is enabled and the cable is disconnected, the RXC clock output (in MII mode) is disabled. RXC clock is enabled after the cable is connected and link is established. 1f.9 1f.8 1f.7 Interrupt Level Enable Jabber AutoNegotiation Complete Enable Pause (Flow Control) PHY Isolate Operation Mode Indication 1 = Interrupt pin active high 0 = Interrupt pin active low 1 = Enable jabber counter 0 = Disable jabber counter 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed 1 = Flow control capable 0 = No flow control capability 1 = PHY in isolate mode 0 = PHY in normal operation 1f.4:2 [000] = still in auto-negotiation [001] = 10Base-T half-duplex [010] = 100Base-TX half-duplex [011] = reserved [101] = 10Base-T full-duplex [110] = 100Base-TX full-duplex [111] = reserved 1f.1 1f.0 Note: 1. RW = Read/Write. RO = Read only. SC = Self-cleared. LH = Latch high. LL = Latch low. KSZ8041NL RW 1 RW RW RW 0 1 0 1f.6 1f.5 RO RO RO 0 0 000 Enable SQE test Disable Data Scrambling 1 = Enable SQE test 0 = Disable SQE test 1 = Disable scrambler 0 = Enable scrambler RW RW 0 0 October 2006 30 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Absolute Maximum Ratings(1) Supply Voltage (VDDPLL_1.8) ............................................... -0.5V to +2.4V (VDDIO_3.3, VDDA_3.3) ................................... -0.5V to +4.0V Input Voltage (all inputs) ............................... -0.5V to +4.0V Output Voltage (all outputs) .......................... -0.5V to +4.0V Lead Temperature (soldering, 10sec.)....................... 260C Storage Temperature (Ts) ..........................-55C to +150C ESD Rating(3) .................................................................. 6kV Operating Ratings(2) Supply Voltage (VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V Ambient Temperature (TA) .............................. 0C to +70C Maximum Junction Temperature (TJ Max) ................. 125C Thermal Resistance (JA) .........................................34C/W Electrical Characteristics(4) Symbol IDD1 IDD2 IDD3 IDD4 TTL Inputs VIH VIL IIN Input High Voltage Input Low Voltage Input Current VIN = GND ~ VDDIO -10 2.0 0.8 10 V V A Parameter (5) Condition Chip only (no transformer); Full-duplex traffic @ 100% utilization Chip only (no transformer); Full-duplex traffic @ 100% utilization Ethernet cable disconnected (reg. 1F.10 = 1) Software power down (reg. 0.11 = 1) Min Typ 53 38 32 4 Max Units mA mA mA mA Supply Current 100Base-TX 10Base-T Power Saving Mode Power Down Mode TTL Outputs VOH VOL |Ioz| Output High Voltage Output Low Voltage Output Tri-State Leakage IOH = -4mA IOL = 4mA 2.4 0.4 10 V V A 100Base-TX Transmit (measured differentially after 1:1 transformer) VO VIMB tr, tf Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot VSET Notes: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. 4. TA = 25C. Specification for packaged product only. 5. Current consumption is for the single 3.3V supply KSZ8041NL device only, and includes the 1.8V supply voltage (VDDPLL_1.8) that is provided by the KSZ8041NL. The PHY port's transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T. 100 termination across differential output 100 termination across differential output 0.95 1.05 2 V % ns ns ns % 3 0 5 0.5 + 0.25 5 0.65 Reference Voltage of ISET Output Jitter Peak-to-peak V 1.4 0.7 ns October 2006 31 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Electrical Characteristics(6) 10Base-T Transmit (measured differentially after 1:1 transformer) VP tr, tf VSQ Notes: 6. TA = 25C. Specification for packaged product only. Peak Differential Output Voltage Jitter Added Rise/Fall Time Squelch Threshold 100 termination across differential output Peak-to-peak 2.2 25 2.8 3.5 V ns ns mV 10Base-T Receive 5MHz square wave 400 October 2006 32 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Timing Diagrams MII SQE Timing (10Base-T) Figure 7. MII SQE Timing (10Base-T) Timing Parameter tP tWL tWH tSQE tSQEP Description TXC period TXC pulse width low TXC pulse width high COL (SQE) delay after TXEN de-asserted COL (SQE) pulse duration Min Typ 400 200 200 2.5 1.0 Max Unit ns ns ns us us Table 6. MII SQE Timing (10Base-T) Parameters October 2006 33 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MII Transmit Timing (10Base-T) Figure 8. MII Transmit Timing (10Base-T) Timing Parameter tP tWL tWH tSU1 tSU2 tHD1 tHD2 tCRS1 tCRS2 Description TXC period TXC pulse width low TXC pulse width high TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC TXD[3:0] hold from rising edge of TXC TXEN hold from rising edge of TXC TXEN high to CRS asserted latency TXEN low to CRS de-asserted latency Min Typ 400 200 200 Max Unit ns ns ns ns ns ns ns 10 10 0 0 4 8 Bit Time Bit Time Table 7. MII Transmit Timing (10Base-T) Parameters October 2006 34 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MII Receive Timing (10Base-T) Figure 9. MII Receive Timing (10Base-T) Timing Parameter tP tWL tWH tOD tRLAT Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to (RXD[3:0], RXER, RXDV) latency Min Typ 400 200 200 Max Unit ns ns ns 182 6.5 225 ns us Table 8. MII Receive Timing (10Base-T) Parameters October 2006 35 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MII Transmit Timing (100Base-TX) Figure 10. MII Transmit Timing (100Base-TX) Timing Parameter tP tWL tWH tSU1 tSU2 tHD1 tHD2 tCRS1 tCRS2 Description TXC period TXC pulse width low TXC pulse width high TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC TXD[3:0] hold from rising edge of TXC TXEN hold from rising edge of TXC TXEN high to CRS asserted latency TXEN low to CRS de-asserted latency Min Typ 40 20 20 Max Unit ns ns ns ns ns ns ns 10 10 0 0 4 4 Bit Time Bit Time Table 9. MII Transmit Timing (100Base-TX) Parameters October 2006 36 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MII Receive Timing (100Base-TX) Figure 11. MII Receive Timing (100Base-TX) Timing Parameter tP tWL tWH tOD tRLAT Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to (RXD[3:0], RXER, RXDV) latency Min Typ 40 20 20 Max Unit ns ns ns 19 1 2 25 3 ns Bit Time Table 10. MII Receive Timing (100Base-TX) Parameters October 2006 37 M9999-102406-1.0 Micrel, Inc. KSZ8041NL RMII Timing Figure 12. RMII Timing - Data Received from RMII Figure 13. RMII Timing - Data Input to RMII Timing Parameter tcyc t1 t2 tod Description Clock cycle Setup time Hold time Output delay Min 4 2 2.8 Typ 20 Max Unit ns ns ns 10 ns Table 11. RMII Timing Parameters October 2006 38 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Auto-Negotiation Timing Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Timing Parameter tBTB tFLPW tPW tCTD tCTC Description FLP Burst to FLP Burst FLP Burst width Clock/Data Pulse width Clock Pulse to Data Pulse Clock Pulse to Clock Pulse Number of Clock/Data Pulse per FLP Burst Min 8 Typ 16 2 100 Max 24 Units ms ms ns 55.5 111 17 64 128 69.5 139 33 s s Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters October 2006 39 M9999-102406-1.0 Micrel, Inc. KSZ8041NL MDC/MDIO Timing Figure 15. MDC/MDIO Timing Timing Parameter tP t1MD1 tMD2 tMD3 Description MDC period MDIO (PHY input) setup to rising edge of MDC MDIO (PHY input) hold from rising edge of MDC MDIO (PHY output) delay from rising edge of MDC Table 13. MDC/MDIO Timing Parameters Min 10 10 Typ 400 Max Unit ns ns ns 222 ns October 2006 40 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Reset Timing The KSZ8041NL reset timing requirement is summarized in the following figure and table. Figure 16. Reset Timing Parameter tsr tcs tch trc Description Stable supply voltage to reset high Configuration setup time Configuration hold time Reset to strap-in pin output Table 14. Reset Timing Parameters Min 10 5 5 6 Max Units ms ns ns ns After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) Interface. October 2006 41 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Reset Circuit The following reset circuit is recommended for powering up the KSZ8041NL if reset is triggered by the power supply. Figure 17. Recommended Reset Circuit The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041NL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up. Figure 18. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output. October 2006 42 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Reference Circuits for LED Strapping Pins The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. Figure 19. Reference Circuits for LED Strapping Pins October 2006 43 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Selection of Isolation Transformer A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance (min.) Leakage inductance (max.) Inter-winding capacitance (max.) D.C. resistance (max.) Insertion loss (max.) HIPOT (min.) Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms Table 15. Transformer Selection Criteria 0MHz - 65MHz 100mV, 100kHz, 8mA 1MHz (min.) Test Condition Magnetic Manufacturer Bel Fuse Bel Fuse (Mag Jack) Bel Fuse (Mag Jack) Delta LanKom Pulse Pulse (low cost) Transpower TDK (Mag Jack) Part Number S558-5999-U7 SI-46001 SI-50170 LF8505 LF-H41S H1102 H1260 HB726 TLA-6T718 Auto MDI-X Yes Yes Yes Yes Yes Yes Yes Yes Yes Number of Port 1 1 1 1 1 1 1 1 1 Table 16. Qualified Single Port Magnetics Selection of Reference Crystal Characteristics Frequency Frequency tolerance (max) Load capacitance (max) Series resistance Value 25 50 20 40 Table 17. Typical Reference Crystal Characteristics Units MHz ppm pF October 2006 44 M9999-102406-1.0 Micrel, Inc. KSZ8041NL Package Information 32-Pin (5mm x 5mm) MLF(R) Package MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. October 2006 45 M9999-102406-1.0 |
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